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block diagram general description features CS5824 28:4 lvds transmitter usa: 4020 moorpark avenue suite 115 san jose, ca, 95117 tel: 408-243-8388 fax: 408-243-3188 sales@myson.com.tw www.myson.com.tw rev.1.4 august 2002 page 1 of 13 myson century, inc. taiwan: no. 2, industry east rd. iii, science-based industrial park, hsin-chu, taiwan tel: 886-3-5784866 fax: 886-3-5784349 four 7-bit serial and one clock lvds channels. compatible with ansi tia/eia-644 lvds standard. wide ckin ranges from 31mhz to 68mhz. fully integrated on-chip pll that provides 7x ckin serial shift clock. pin selectable for rising or falling edge trigger. support power-down mode. 5v/3.3v tolerant data input. single 3.3v supply operation. cmos low power consumption. functional compatible with ds90c385. available in 56-pin tssop package. parallel-in serial-out 7-bit shift register parallel-in serial-out 7-bit shift register parallel-in serial-out 7-bit shift register shift/load_n din clk phase lock loop r/f clk 7xclk shift/load_n control logic d19,d20,d21,d22, d27,d5,d10,d11, rf ckin shtdn en ckop ckon CS5824 din clk din clk shift/load_n shift/load_n en y3p y3n en y2p y2n en y1p y1n en y0p y0n parallel-in serial-out 7-bit shift register din clk shift/load_n d0,d1,d2,d3, d4,d6,d7 d8,d9,d12,d13, d14,d15,d18 d24,d25,d26 d16,d17,d23 the CS5824 receives four sets of 7-bit data in cmos logic level and converts them into four low- voltage differential signaling (lvds) serial channels. the 7-bit input data is referenced to the ckin signal. the rf pin selects either rising or falling edge trigger of ckin. parallel to serial conversion is performed by a 7x internal generated clock reference using on- chip pll using ckin. a copy of ckin but phase- locked to the output serial streams, clkout, is also converted to the fifth lvds channel. the CS5824 offers a reliable communication media using lvds signaling and provides low emi dealing with wide, high-speed ttl interfaces. this is especially attractive for interfaces between gui controller and display systems such as lcd panels for svga/xga/sxga applications. .com .com .com .com 4 .com u datasheet
CS5824 page 2 of 13 pin connection diagram figure-1 56-pin tssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vdd d5 d6 d7 vss d8 d9 d10 vdd d11 d12 d13 vss d14 d15 d16 rf d17 d18 d19 vss d20 d21 d22 d23 vdd d24 d25 CS5824 d4 d3 d2 vss d1 d0 d27 lvds_vss y0m y0p y1m y1p lvds_vdd lvds_vss y2m y2p ckom ckop y3m y3p lvds_vss pll_vss pll_vdd pll_vss shtdn ckin d26 vss 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 .com .com .com .com .com 4 .com u datasheet
CS5824 page 3 of 13 pin description name i/o description d0,d1,d2,d3,d4, d6,d7 i parallel data input for y0 lvds channel. d[0] is lsb and d[7] is msb. msb is shifted out first. d8,d9,d12,d13, d14,d15,d18 i parallel data input for y1 lvds channel. d[8] is lsb and d[18] is msb. d19,d20,d21,d22 ,d24,d25,d26 i parallel data input for y2 lvds channel. d[19] is lsb and d[26] is msb. d27,d5,d10,d11, d16,d17,d23 i parallel data input for y3 lvds channel. d[27] is lsb and d[23] is msb. ckin i parallel input clock.this clock signal is used for parallel data reference. it is also used by the on-chip pll to generate the 7x shift clock for parallel to serial conversion. rf i rise/fall select. this pin selects the polarity of the ckin edge for data input. rf = 1 selects ckin rise edge, and rf = 0 selects ckin fall edge. shtdn i shutdown control (low active). when shtdn is low, the internal pll is put into inhibit mode and all lvds output channels are shut off. this also resets all internal registers. for normal operation, shtdn should be set to high. y0p, y0n o y0 lvds channel output. these are differential lvds outputs for y0 channel corresponds to d0, d1, d2, d3, d4, d6, d7. y1p, y1n o y1 lvds channel output. these are differential lvds outputs for y1 channel corresponds to d8, d9, d12, d13, d14, d15, d18. y2p, y2n o y2 lvds channel output. these are differential lvds outputs for y2 channel corresponds to d19, d20, d21,d22, d24, d25, d26. y3p, y3n o y3 lvds channel output. these are differential lvds outputs for y3 channel corresponds to d27, d5, d10, d11, d16, d17, d23. ckop, ckon o clock lvds channel output. these are differential lvds output for the replica of ckin signal. ckop and ckon are derived from the internal phase lock loop and phase aligned with the serial data output and can be used by the lvds receiver for reference edge. pll_vdd p power supply for pll circuit. pll_vss p power ground for pll circuit. lvds_vdd p power supply for output buffer circuits. lvds_vss p power ground for output buffer circuits. vdd p power supply for internal circuits. vss p power ground for internal circuits. .com .com .com .com .com 4 .com u datasheet
CS5824 page 4 of 13 functional description control logic there are two modes in this circuit. one is normal mode, and another is power down mode. two modes are controlled by the control signal ?shtdn?. if shtdn is high, the circuit is in the normal mode, else if low, the circuit is in the power down mode. in the power down mode, every block is off to make sure the least power consumption. 7 x clk pll 7 x clk pll, which is a phase lock loop, generates seven times clock of ckin. the signal ?rf? indicates that the input data (d0 ~ d27) is rising edge or falling edge trigger by ckin. if rf=1, it is rising edge trigger, else if rf=0, it is falling trigger. this seven times clock of ckin is used by the parallel ~ load 7 bit shift register. 7 x clk pll also generate the control signal ?shift/load ?. this signal is also used by the parallel ~ load 7 bit shift register to indicate when to load data or shift data. parallel ~ load 7 bit shift register this block transfers 7 bits parallel data into one bit series data out. it is controlled by shift/load . if this control signal is low, the data are loaded into shift registers. next, the shift/load turns high to shift data from shift register to output buffer seven times. one load and then seven shift. ref: there are two properties in this block. one is that it supports reference voltage to fine the output?s common mode voltage. another is that it generates about (4ns ~6ns) pulse width?s power on reset signal. when power on, all block would be reset by power on reset signal to make sure that the circuit would not stuck-at some situation we do not care. output buffer there are four data output buffers and one clock output buffer. output buffer generates differential pair output that swing is under 500 ~ 900mv, and common-mode voltage is under 1.125v ~ 1.375v. .com .com .com .com .com 4 .com u datasheet
CS5824 page 5 of 13 recommended operating conditions timing requirements symbol parameter min typ max unit v cc supply voltage 3 3.3 3.6 v v ih high-level input voltage 2 - - v v il low-level input voltage - - 0.8 v z l differential load impedance 90 - 132 ? t a operating free-air temperature 0 - 70 c symbol parameter min typ max unit t c input clock period 14.7 32.4 ns t w pulse duration, high-level input clock 0.4t c 0.6t c ns t t transition time, input signal 5 ns t su setup time, data, d0~d27 valid before ckin (rf = 0) or ckin (rf = 1) 3ns t h hold time, data, d0~d27 valid after ckin (rf = 0) or ckin (rf = 1) 1.5 ns .com .com .com .com .com 4 .com u datasheet
CS5824 page 6 of 13 dc characteristics note: all typical values are at v cc = 3.3v, t a = 25 c. symbol parameter condition min typ max unit v it input threshold voltage -1.4- v ? v od ? differential steady-state output voltage magnitude rl = 100 ? 247 340 454 mv ?? v od ? change in the steady-state differential output voltage magnitude between opposite binary states -1050mv v oc(ss) steady-state common-mode output voltage 1.125 - 1.375 v v oc(pp) peak-to-peak common-mode output voltage - 80 150 mv i ih high-level input current v ih = v cc -- 20 a i ih - shtdn high level input current for shtdn pin v ih = v cc -- 10 a i il low-level input current v il = 0 -- 10 a i os short-circuit output current v o(yn) = 0 -- 24 ma v od = 0 -- 12 ma i oz high-impedance output current v o = 0 to v cc -- 10 a i cc(avg) quiescent supply current (average) power down shtdn = 0 --250 a enabled, r l = 100 ? (4 places) gray_scale pattern v cc = 3.3v, t c = 15.38ns - 40 60 ma enabled, r l = 100 ? (4 places) worst_case pattern t c = 15.38ns - 50 75 ma c i input capacitance - 3-pf .com .com .com .com .com 4 .com u datasheet
CS5824 page 7 of 13 ac characteristics symbol parameter condition min typ max unit t 0 cko to bit 0 t c = 15.38 ns -0.2 0 0.2 ns t 1 cko to bit 1 1/7t c -0.2 - 1/7t c +0.2 ns t 2 cko to bit 2 2/7t c -0.2 - 2/7t c +0.2 ns t 3 cko to bit 3 3/7t c -0.2 - 3/7t c +0.2 ns t 4 cko to bit 4 4/7t c -0.2 - 4/7t c +0.2 ns t 5 cko to bit 5 5/7t c -0.2 - 5/7t c +0.2 ns t 6 cko to bit 6 6/7t c -0.2 - 6/7t c +0.2 ns t skew output skew -0.2 - 0.2 ns ? t c (o) cycle time, output clock jitter - 100 -ps t w pulse duration, high-level output clock - 4/7t c -ns t t transition time, differential output voltage (t r or t f ) 260 700 1500 ps t enable enable time, shtdn to phase lock (yn valid) -1-ms t disable disable time, shtdn to off state (cko low) - 250 - ns .com .com .com .com .com 4 .com u datasheet
CS5824 page 8 of 13 note: maximum value of t r , t f = 5ns figure-2 setup and hold time definition (a) schematic (b) waveforms figure-3 test load and voltage definitions for lvds outputs dn t h t su ckin (rf=1) ckin (rf=0) yp ym 49.9 ? 1%(2 places) c l =10pf max (2 places) v oc v od 100% 80% 0v 20% 0% v od (h) v od (l) t r t f v oc (pp) v oc (ss) v oc (ss) 0v .com .com .com .com .com 4 .com u datasheet
CS5824 page 9 of 13 test pattern figure-4 16-grayscale testing pattern waveforms figure-5 the worst-case testing pattern waveforms figure-6 timing waveform?s definitions ckin d0, 8, 16 d1, 9, 17 d2, 10, 18 d3, 11, 19 d4-7, 12-15, 20-23 d24-27 ckin even dn odd dn cko yn t 1 t 2 t 3 t 4 t 5 t 6 t 0 .com .com .com .com .com 4 .com u datasheet
CS5824 page 10 of 13 typical characteristics figure-7 enabled time waveforms figure-8 disabled time waveforms ckin shtdn yn t enable invalid valid valid valid note: rf=1 ckin cko shtdn note: rf=1 t disable .com .com .com .com .com 4 .com u datasheet
CS5824 page 11 of 13 package outline (56-pin tssop) note: 1. ordering information; 35 units per tube, and 2500 units per tape on reel. note: 2. the CS5824 products keep using the original century logo. symbol dimensions in millimeters dimensions in inches min nom max min nom max a 1.05 - 1.20 0.041 - 0.047 a1 0.05 - 0.15 0.002 - 0.006 a2 - 0.90 - - 0.035 - b 0.17 0.20 0.27 0.007 0.008 0.010 c 0.09 0.15 0.20 0.004 0.006 0.008 d 13.90 14.00 14.10 0.547 0.551 0.555 e 7.80 8.10 8.40 0.307 0.319 0.330 e1 6.00 6.10 6.20 0.236 0.240 0.244 e - 0.50 - - 0.0197 - l 0.50 - 0.75 0.020 - 0.030 0 - 7 0 - 7 e e1 e a1 a2 a d l c b .com .com .com .com .com 4 .com u datasheet
CS5824 page 12 of 13 packaging specification dimension standard packing quantity reel for taping unit: mm symbol b0 d0 e f k1 p0 p1 p2 t1 t2 w unit: mm 14.5 1.5 +0.1 -0 1.75 0.1 11.5 0.05 1.3 max 4 0.2 12.0 0.1 2 0.05 0.3 0.05 1.8 max 24.0 0.3 carrier tape width reel size pocket pitch leader no. of pockets end no. of pockets quantity (pcs/reel) 24mm 330mm 4mm 20 30 2500 abcdew1w2 330 +1 -4 100 0.1 13 +0.5 -0.2 20.2 0.8 2.0 0.5 24.8 +0.3 -0.2 30.2 max p2 p0 p1 a a b b e f w d0 d0 r0.3 typical section a-a t1 section b-b chamfer t2 k1 r0.1 r0.3max b0 6.0 6.8 8.6 3.0 3.4 2.0 3.0 e d c a b w1 w2 .com .com .com .com .com 4 .com u datasheet
CS5824 page 13 of 13 leader part and taped end approval supplier for packing material ordering information part number item supplier carrier tape advantek cover tape advantek plastic reel advantek prefix part type package type cs 5824 n:tssop vacant position 20 0 top cover tape tape end 30 vacant position leader part pin1 unwinding direction .com .com .com .com 4 .com u datasheet

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